Prototyping Digital Computing-in-Memory (CiM) on FPGAs: Challenges and Considerations

Researchers are exploring the prototyping of digital Computing-in-Memory (CiM) concepts on FPGA BRAMs/URAMs to minimize AXI bus overhead in custom RISC-V SoC designs with integrated AI accelerators. The primary challenge lies in maintaining high performance (Fmax) and avoiding routing complexities when mapping digital CiM logic onto FPGAs. This approach is being considered for a Keyword Spotting m

Sector: Electronic Labour | Confidence: 95%
Source: https://www.reddit.com/r/chipdesign/comments/1rg5hd2/prototyping_digital_computinginmemory_cim/

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Council (3 models): Researchers are prototyping digital Computing-in-Memory (CiM) on FPGAs to minimize AXI bus overhead in custom RISC-V SoC designs with AI accelerators, facing challenges in maintaining high performance and avoiding routing complexities. The tension between FPGA flexibility and CiM performance optimizations highlights broader hardware acceleration trade-offs in AI workloads, particularly for edge applications like keyword spotting. Practical implementation reveals significant performance and routing complexities that may negate CiM's theoretical advantages, underscoring the challenges in optimizing hardware for specialized AI tasks. Cross-sector impacts include influencing real-time financial data processing and enabling edge AI applications in smart infrastructure, reducing cloud reliance.
Cross-sector: Finance, Real Infrastructure

  ? How do current FPGA-based CiM implementations compare to ASIC-based solutions in terms of energy efficiency and scalability?
  ? What are the key bottlenecks in mapping CiM logic onto FPGAs, and how are researchers addressing them?
  ? What are the potential performance benefits of using CiM concepts on FPGAs compared to traditional MAC tree architectures?

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